A unified high-performance and memory-efficient architecture is proposed to perform 5/3 DWT and 9/7 DWT in JPEG2000 with a novel modified lifting algorithm.By applying the proposed lifting scheme

the transposing buffer between the row processor and the column processor is eliminated

resulting in a reduction of the internal memory requirement.For an N×N image

only 2N internal memory is required for 5/3 DWT and 4N is required for 9/7 DWT to perform 2D DWT with the critical path limited by one multiplier delay by employing the pipeline technique.Compared with the existing 2D DWT architectures

the proposed 2D DWT architecture has the advantage of regular structure

low memory requirement and high system performance.The proposed architecture was described with Verilog HDL language and verified to be correct in ModelSim.It was also synthesized

placed and routed on an Altera StratixⅡ FPGA EP2S60F1024C4 using Quartus Ⅱ version 5.0 toolset.The experimental result shows that 1 284 ALUTs are utilized with memory size of 4 K words for 1 024×1 024 image and the operating frequency can be up to 172.56 MHz.