This paper presents a design of the hidden surface removal hardware module based on the Cache and Hierarchical Z-Buffer algorithm. The hardware module can save bandwidth while increasing speed and improving efficiency of hidden surface removing

which is suitable for bandwidth-limited on-chip 3D graphics rendering system. The design optimizes the Z Cache structure to acquire high hit rate

and uses one-level Hierarchical Z-Buffer algorithm to enhance the effect

meanwhile affiliates the Fast Z Clear structure to save bandwidth. The design has been described the RTL models and has passed the simulation. Experimental results show savings of about 30％ of the bandwidth

speed and efficiency of removal up to 20％ at best.