A high throughput inverse transform IP core for H.264/AVC was proposed in this paper. The improved T architecture was presented to synchronize three different transforms and inverse ZigZag scan module. By applying time multiplexing buffer management to inverse Hadamard transform

we efficiently reduce its latency. Separability property of IDCT is also utilized to minimize its area. At last

the results of synthesis are given with Xilinx Virtex2 while XC2V6000 as the target device. The simulation performance shows that the design can effectively support the real time decoding of 1080i 50Hz HD stream.