A High-performance Hardware Implementation of the H. 264  Transformation and Quantization Oriented to FPGA

doi:10.11834/jig.2006011281

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A High-performance Hardware Implementation of the H. 264 Transformation and Quantization Oriented to FPGA
Vol. 11, Issue 11, Pages: 1636(2006)
Published：2006
DOI： 10.11834/jig.2006011281
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DOI：

A High-performance Hardware Implementation of the H. 264 Transformation and Quantization Oriented to FPGA[J]. Journal of Image and Graphics, 2006, 11(11): 1636. DOI： 10.11834/jig.2006011281.

摘要

针对H．264视频标准中一个功能频繁调用的变换量化模块，提出了一种高性能的FPGA硬件实现方法。并完成了其硬件原型的设计。该硬件原型包含了从残差形成到宏块重建的变换量化全过程。其可以构成DSP的协处理器，用于完成H．264实时编解码。该硬件原型根据算法特点和数据流特点，采用了流水线控制策略和分时复用技术，同时合理利用FPGA片内资源，从而提高了系统性能。仿真结果表明。该设计能满足高清数字视频的实时处理应用。

Abstract

This paper presents a high-performance FPGA hardware implementation of the H.264 transformation and quantization.The hardware prototype is composed of the whole processes from obtaining residual error to Macro-Block reconstruction

and it can be used as a co-processor of DSP to fulfill H.264 real-timing CODEC.Based on the characteristics of algorithms and data flow

the hardware prototype adopts pipeline strategy and time division multiplexing(TDM) technology

and utilizes FPGA dedicated resources reasonably

that enhances the performance of the hardware prototype greatly.The simulation results show that the design can satisfy the real-time constraints required by HDTV applications.