Due to its excellent compression rate and high image quality

H.264 is widely applied in many regions

such as real-time internet video communication

digital television broadcast

HDTV and so on. As a key component of the H.264 coding framework

integer discrete consine transform(IDCT) and quantification module takes on the rule of reducing the correlation coefficients of input data

which is an important pre-processing before the entropy coding. The normal realizations are based on software or hardware co-processor

in which way speed and throughput are limited. As a contrast

realization based on hardware can make up these shortages. In this paper

an FPGA implementation of integer discrete consine transform and quantification for H.264 compression is introduced

which is based on a high throughput structure and is accomplished by register-transfer level (RTL) description. The whole design is tested on the Cyclone Ⅱ-based development board

DE Ⅱ. The resource cost is 10489 LEs. Its maximal work frequency is 184.88MHz

the maximal throughput is 2958Mpixels/s

and it can process a 4×4 input data within a single clock period.