High speed and low cost architecture of CAVLC encoder

doi:10.11834/jig.20110219

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High speed and low cost architecture of CAVLC encoder
Vol. 16, Issue 2, Pages: 202-208(2011)
Published Online：03 March 2011，

Published：2011
DOI： 10.11834/jig.20110219
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DOI：

High speed and low cost architecture of CAVLC encoder[J]. Journal of Image and Graphics, 2011, 16(2): 202-208. DOI： 10.11834/jig.20110219.

摘要

变长编码是视频编码中的关键技术之一，计算量大。提出一种应用于H.264/AVC的高速有效的CAVLC编码器结构。采用基于预处理的查找方法，改进了查找表结构；利用算术计算替代查找表，且通过展开和共享技术对算术表达式进行优化；其他方面也做了面积上的优化。实验结果表明，在133MHz的频率约束下，采用SMIC 018μm CMOS工艺进行逻辑综合，所需的逻辑门数为8723，能满足高清视频1920×1088-30帧/s实时编码吞吐量的要求，具有实际应用价值。

Abstract

Variable Length Coding is one of the key technologies in video coding with large computation requirement. A high speed and efficient VLSI architecture for H.264/AVC CAVLC is proposed. A new look-up table algorithm based on the pre-processing greatly optimizes look-up table structure. An arithmetic compute method is exploited to replace look-up table

and the arithmetic expression is optimized with technology of unfolding and share. Some area optimization is done in the other part. Experimental result shows that for logic synthesis

the hardware cost of the proposed design is 8723 logic gates by using SMIC 0.18μm CMOS technology at the clock frequency constraint of 133MHz. The new architecture can meet the requirement for the real-time processing for High-definition 1920×1088-30fps video with less hardware cost. So it has practical application value.