Variable Length Coding is one of the key technologies in video coding with large computation requirement. A high speed and efficient VLSI architecture for H.264/AVC CAVLC is proposed. A new look-up table algorithm based on the pre-processing greatly optimizes look-up table structure. An arithmetic compute method is exploited to replace look-up table

and the arithmetic expression is optimized with technology of unfolding and share. Some area optimization is done in the other part. Experimental result shows that for logic synthesis

the hardware cost of the proposed design is 8723 logic gates by using SMIC 0.18μm CMOS technology at the clock frequency constraint of 133MHz. The new architecture can meet the requirement for the real-time processing for High-definition 1920×1088-30fps video with less hardware cost. So it has practical application value.