基于Cache和层次Z缓存算法的3维图形深度消隐硬件设计和实现

钟伟; 郭立; 杨毅

doi:10.11834/jig.20090724

计算机图形学 | 浏览量 : 0 下载量: 247 CSCD: 0

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基于Cache和层次Z缓存算法的3维图形深度消隐硬件设计和实现
Design and Implementation of Hidden Surface Removal Hardware Based on Cache and Hierarchical Z-Buffer Algorithm for 3D Graphics
2009年14卷第7期页码：1392
纸质出版：2009
DOI： 10.11834/jig.20090724
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钟伟, 郭立, 杨毅. 基于Cache和层次Z缓存算法的3维图形深度消隐硬件设计和实现[J]. 中国图象图形学报, 2009,14(7):1392. DOI： 10.11834/jig.20090724.

Design and Implementation of Hidden Surface Removal Hardware Based on Cache and Hierarchical Z-Buffer Algorithm for 3D Graphics[J]. Journal of Image and Graphics, 2009, 14(7): 1392. DOI： 10.11834/jig.20090724.

摘要

为了在3维图形渲染硬件系统中节省带宽和提高消隐效率，基于Cache和层次Z缓存算法（hierarchical Z-buffer，HZB），设计了一个深度消隐硬件模块。该硬件模块主要面向带宽有限的片上3维图形渲染系统，其在节省带宽的同时，还可加快消隐速度和提高消隐效率。该模块通过设计优化Z Cache结构来获得较高命中率，并采用了1级层次Z缓存算法，以提高消隐效果，同时加入了快速Z清除(Fast Z Clear）结构

以节省带宽。该设计已通过RTL级建模和仿真验证。实验结果表明，该新的硬件可节省大概30％的带宽，消隐速度和效率最多可提高20％。

Abstract

This paper presents a design of the hidden surface removal hardware module based on the Cache and Hierarchical Z-Buffer algorithm. The hardware module can save bandwidth while increasing speed and improving efficiency of hidden surface removing

which is suitable for bandwidth-limited on-chip 3D graphics rendering system. The design optimizes the Z Cache structure to acquire high hit rate

and uses one-level Hierarchical Z-Buffer algorithm to enhance the effect

meanwhile affiliates the Fast Z Clear structure to save bandwidth. The design has been described the RTL models and has passed the simulation. Experimental results show savings of about 30％ of the bandwidth

speed and efficiency of removal up to 20％ at best.

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