In this paper

a hardware algorithm for graphics rasterizer on embedded platform is presented. By dividing the pixels in the triangles bounding box into a number of regular tiles

the algorithm do the scan conversion

pixel interpolation and projective correction on the basis of tile architecture. After a lot of optimization

the algorithm is implemented and tested on FPGA. As compared with the traditional algorithm

the algorithm presented in this paper has increased the pixel hit rate

and reduced the computational complexity

as well as effectively reduced the hardware cost. Testing results show that

the quality of the algorithms rendered images has reached the level of OpenGLES 1.1.In general scene

the rendering speed reached 30 fps

meeting the requirements of real-time rendering. In terms of the synthesized hardware resources

it is small within 5 545 slices on Xilinx FPGA Vertex2P xc2vp30-7ff89.