The goal of stereo vision is to recover the three-dimensional information of a scene

and the core of stereo vision is to find the corresponding pixels.However

the correspondence search is too time-consuming for high speed robot vehicles autonomous navigation

even if state-of-art general-purpose processors are used to accelerate it.Aiming at this problem

this paper presents a design scheme for binocular stereo vision system based on field programmable gate arrays(FPGA)

its hardware structure is introduced

and a fast zero mean sum of squared differences(ZSSD) stereo matching algorithm is discussed.Moreover

a pixel-serial and window-parallel architecture based on FPGA processor is proposed to achieve ZSSD matching algorithm

which is suitable for parallel processing.The stereopsis is captured by two same decoder chips.After rectification and ZSSD matching implemented by FPGA

dense disparity map is computed and sent to general-purpose computer by PCI bus.The proposed scheme is very robust and exhibits great performance

such as high speed.And the hardware system has high stability and reliability.In addition

this scheme is also applicable to fast and real-time processing of other conventional area-based stereo matching algorithms

such as sum of absolute differences(SAD)

sum of squared differences(SSD)

etc.