A novel hardware architecture of zerotree coding is presented for MPEG 4 texture coding. Under the architecture

two bottlenecks in zerotree coding are handled. The recursive scans of parent and children coefficients are avoided

and the skips of the significant coefficients and their descendents are fulfilled easily. The label coefficient is implemented in one scan by exploiting the features of MPEG 4 zerotree symbol alphabet. A ZTR address buffer is designed to simplify skipping processing of significant coefficients

and to fasten the search for the descendent coefficients of ZTR/VZTR nodes. A preprocessing unit of significant coefficients is also proposed with bit or and bit not and logic circuits

which is essential for independent coding of individual bitplane. The architecture is tested in a platform with FPGA chips. With the application of MPEA 4

the design can be applied to various equipments as an independent IP core. A parallel structure needs to implement for applications with stricter time requirement.