In GPUs based on TBR architecture

the efficiency of triangle raster greatly influences chip performance. Traditional algorithms generate severalredundant pixels and lose the advantages of TBR architecture. A high-efficiency triangle raster algorithm is proposed in this paper. The features of TBR architecture are fully utilized in this algorithm. The draw parameters of each tile are calculated in the pre-processing stage. The position relationship between the triangle and the tile boundary is obtained. All data are committed to memory. In the raster stage

the Bresenham algorithm is used to obtain all the horizontal scan lines in every tile untilall pixels of the scan lines are eventually generated. After theoretical analysis

the raster efficiency of the raster operation can reach 83% and even approach 100%

depending on the triangle shape. The function and performance of this algorithm are evaluated with a FPGA proto type verification system. To adapt to the TBR architecture

a new triangle raster algorithm is proposed in this paper. The pixel fill rate is equivalent to ATI M9

which has twice the clock rate. Therefore

the algorithm can achieve high raster efficiency.